• Image capture and processing.
• Communication between board components (image sensors, temperature sensors, memory), the OBC Athena, and the Electronic Power Supply (EPS).

• On-board Temperature Detection and Sensing,
• Voltage Domain Buffering:
  • Signals from different power domains are buffered to prevent unwanted powering of components. Connections to different power domains are present, and are therefore buffered.
• Overcurrent Protection:
  • ICs onboard Electra enact mechanisms that prevent damage to components from single-event latch-up damage (SEL) caused by extraterrestrial radiation effects (i.e. solar flare, cosmic radiation). Such events draw exceedingly high currents to components which can cause heavy damage.

• Radiometric resolution of >= 8 bits/pixel.
  • Research shows that there is no benefit past 8 bits/pixel with NDVI in mind.
•  Consumes less than 10W

The Altera Cyclone V FPGA SoC field-programmable gate array from Intel is used. This can be thought of as the brains of Electra — all the components of Electra communicate to and through this central FPGA and take action based on this data. The device also contains a dual-core microcontroller for software implementation, which allows Electra to communicate to communicate image data to Ex-Alta 2’s OBC Athena. In the case of Overcurrent/SEL, the cubesat Electronic Power System (EPS) will power cycle Electra, and re-boot the FPGA safely.

Electra houses and collects reflectance data from two image sensors in two different groups of wavelength bands: visible + near infrared (VNIR), and shortwave infrared (SWIR).

VNIR data is obtained from the CMV4000 high-speed 4.2 Megapixel CMOS image sensor from ams. SWIR data is obtained from the G11478-512WB linear pixel array from Hamamatsu.

Electra is equipped with six TMP421 temperature sensors that monitor areas that dissipate lots of power. Data is communicated to the central FPGA SoC (Cyclone V) for later transmission to the ground as part of generic housekeeping and monitoring data.

Electra holds 4Gb DDR3 933MHz SDRAM interfaced with the Cyclone V FPGA SoC. The memory is used to buffer reflectance data from the dual image sensors before it is sent to Athena (Ex-Alta 2’s On-Board Computer).